iverilog.icarus.comIcarus Verilog

Search this site Home Quick Links Add-ons Notable Links Support Bugs Support Providers Donations Media Home Welcome to the home page for . This is the source for your favorite free implementation of Verilog! What Is ? is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly . This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2005. This is a fairly large and complex standard, so it will take some time to fill all the dark alleys of the standard, but that's the goal. is a work in progress, and since the language standard is not standing still either, it probably always will be. That is as it should be. However, I will make stable releases from time to time, and will endeavor to not retract any features that appear in these stable releases. The quick links above will show the current stable release. The main porting target is Linux, although it works well on many similar operating systems. Various people have contributed precompiled binaries of stable releases for a variety of targets. These releases are ported by volunteers, so what binaries are available depends on who takes the time to do the packaging. has been ported to That Other Operating System, as a command line tool, and there are installers for users without compilers. You can compile it entirely with free tools, too, although there are precompiled binaries of stable releases. Where is ? NOTE: This is a quick summary of where to get . for more complete download and install instructions, look --> here . The Current release is available in source and a variety of binary forms in the FTP directory < ftp://icarus.com/pub/eda/verilog/v10/ >. Updates to the stable release may be made from time to time to fix problems, but there should be no compatibility issues within this version series. This will continue to be maintained until rendered obsolete by a new stable release. Development snapshots are made fairly often, and made available in the FTP directory < ftp://icarus.com/pub/eda/verilog/snapshots >. The files are gzip compressed tar files that contain the source and makefiles. These snapshots follow development progress, and, although the latest features are included in this source, compatibility from snapshot to snapshot is not guaranteed. And finally, the current "git" repository is available for read-only access via anonymous git cloning. This allows for those who which to track my progress and contribute with patches timely access to the most bleeding edge copy of the source. Access the git repository of Icarus Verilog with the commands: git clone git://github.com/steveicarus/iverilog.git (Note: The older CVS repository is obsolete.) From here, you can use normal git commmands to update your source to the very latest copy of the source. See the Installation Guide for details on how to access and compile the git repository. A Test Suite? There is also a test suite available. The test suite is also accessible as the ivtest github.com project, available here: < https://github.com/steveicarus/ivtest >. Access the git repository of the test suite with the command: git clone git://github.com/steveicarus/ivtest.git Since the test suite is simply an ongoing accumulation of tests, there are not typically any releases, per se. Only the git source. Who is ? The main compiler is written by (and copyright) Stephen Williams . That's me. In fact, I'm still working on it, and will continue to work on it for the foreseeable future. I'm a software engineer specializing in device drivers and embedded systems, although I have some limited hardware design experience. Even so, I am a software engineer writing software for hardware designers, so expect the occasional communications glitch:-) There is also a cast of characters who have contributed patches, tests, and various bits to the project. See the git logs to get an idea of the breadth of the contributor base. I'll be adding a credits page someday, although the source distributions do in general name names. The mailing lists for Icarus Verilog are hosted by sourceforge.net , so go there for mailing list archives and instructions on joining; but it is often discussed in the gEDA mailing lists as well. See the gEDA home page for information about that project, and information about how to join the mailing list. While you are browsing the gEDA web site, notice all the other nifty EDA related tools that are there. While is not literally part of the gEDA project, we cooperate and try to support each other. Icarus Verilog users are often gEDA users as well. Sign in | Recent Site Activity | Report Abuse | Print Page | Powered By Google Sites...